1. Field of the Invention
The present invention relates generally to a variable length packet switching system having a plurality of ports, and more particularly to a variable length packet switching system, in which a plurality of chips for dividing data into units of a predetermined length including overheads are employed in parallel to perform switching, and multiplexing/demultiplexing, buffering and format conversion are carried out by the port upstream/downstream of the chips, thereby allowing high-speed switching to be performed in a non-blocking manner without the intervention of software, and enabling the expansion of its capacity by the accommodation of various signals.
2. Description of the Prior Art
In a conventional packet switching system, a switch chip such as the MASCON developed by the Electronics and Telecommunications Research Institute (ETRI) has sixteen 8-bit input/output ports. In order to switch the sixteen 16-bit ports using the MASCON chip, two MASCON chips are arranged in parallel and 16-bit input/output data are switched by the two MASCON while being divided into upper and lower 8-bit data. Such a conventional switching system is provided with a 16-bit backplane, there is a disadvantage that the number of signals is increased. The current technology can provide a 10 Gbps switching system that is operated at 50 MHz and switches 16 ports with 16 bits. Additionally, in accordance with the technology, a 32-bit backplane is provided and 4 MASCON chips are used for each byte, so a switching system can be operated at 50 MHz while doubling the port speed of a switching board, e.g., up to 1.25 Gbps. However, the conventional switching system cannot perform switching for more than 32 ports. Additionally, there is a problem that the conventional switching system can be used only for ATM cells.